Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Abstract Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve quality, compared with conventional automatic pattern generation (ATPG) approaches, which target only at the boundaries of cells. The CAT methodology consists two stages. Stage 1, based on dedicated analog simulation, characterization per cell identifies cell-level detects cell-internal defect; this detection information is encoded in a defect matrix (DDM). In 2, DDMs as inputs, cell-aware ATPG generates chip-level patterns circuit design that build up interconnected instances This paper focuses characterization, both quality and cost are determined set identified simulated tool flow. With aim achieve best we first propose an approach identify comprehensive set, referred full , potential open- short-defect locations layout. However, can be large even for single cell, making time simulation 1 unaffordable. Subsequently, reduce time, collapse compact serves input simulation. stored diagnosis failure analysis. inspecting results, method verify and, if necessary, compensate same level defects. For 351 combinational Cadence’s GPDK045 45nm library, simulate 5.4% from total, via linear extrapolation would reduced 96.4%